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Philips Semiconductors
Product specification
Insulated Gate Bipolar Transistor Protected Logic-Level IGBT
GENERAL DESCRIPTION
Protected N-channel logic-level insulated gate bipolar power transistor in a plastic envelope suitable for surface mount applications. It is intended for automotive ignition applications, and has integral zener diodes providing active collector voltage clamping and ESD protection up to 2 kV.
BUK866-400 IZ
QUICK REFERENCE DATA
SYMBOL PARAMETER V(CL)CER VCEsat IC Ptot ECERS Collector-emitter clamp voltage Collector-emitter on-state voltage Collector current (DC) Total power dissipation Clamped energy dissipation MIN. TYP. MAX. UNIT 350 400 500 2.2 20 100 300 V V A W mJ
PINNING - SOT404
PIN 1 2 3 tab gate collector emitter collector DESCRIPTION
PIN CONFIGURATION
mb
SYMBOL
c
g
2 1 3
e
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VCE VCE VGE IC IC ICM ICLM ECERS ECERR EECR Ptot Tstg Tj PARAMETER Collecter-emitter voltage Collector-emitter voltage Gate-emitter voltage Collector current (DC) Collector current (DC) Collector current (pulsed peak value, on-state) Collector current (clamped inductive load) Clamped turn-off energy (non-repetitive) Clamped turn-off energy (repetitive) Reverse avalanche energy (repetitive) Total power dissipation Storage temperature Operating Junction Temperature CONDITIONS tp 500 s Continuous Tmb = 100 C Tmb = 25 C Tmb = 25 C; tp 10 ms; VCE 15 V 1 k RG 10 k Tmb = 25 C; IC = 10 A; RG = 1 k; see Figs. 23,24 Tmb = 125 C; IC = 8 A; RG = 1 k; f = 50 Hz; t = 60 min. IE = 1 A; f = 50 Hz Tmb = 25 C MIN. -20 -55 -40 MAX. 500 50 12 10 20 25 10 300 125 5 125 150 150 UNIT V V V A A A A mJ mJ mJ W C C
ESD LIMITING VALUE
SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage CONDITIONS Human body model (100 pF, 1.5 k) MIN. MAX. 2 UNIT kV
December 1996
1
Rev. 1.100
Philips Semiconductors
Product specification
Insulated Gate Bipolar Transistor Protected Logic-Level IGBT
THERMAL RESISTANCES
SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS minimum footprint, FR4 board (see Fig. 26).
BUK866-400 IZ
TYP. 50
MAX. 1.0 -
UNIT K/W K/W
STATIC CHARACTERISTICS
Tmb = 25 C unless otherwise specified SYMBOL V(BR)CG V(BR)EC V(BR)GES VGE(TO) VGE(TO) ICES ICES IEC IEC IGES VCEsat PARAMETER Collector-gate zener breakdown voltage Reverse collector-emitter breakdown voltage Gate-emitter breakdown voltage Gate threshold voltage Gate threshold voltage Zero gate voltage collector current Zero gate voltage collector current Reverse collector current Reverse collector current Gate emitter leakage current Collector-emitter on-state voltage CONDITIONS 2 mA -IG 5 mA; -40 Tj 150C IE = 10 mA IG = 1 mA VCE = VGE; IC = 1 mA VCE = VGE; IC = 1 mA; -40 Tj 150C VCE = 50 V; VGE = 0 V; Tj = 25 C Tj = 125 C VCE = -20 V VCE = -20 V; Tj = 125C VGE = 6 V Tj = 150C VGE = 4.5 V; IC = 8 A VGE = 3.5 V; IC = 6 A; -40 Tj 150C MIN. 350 20 12 1 0.6 TYP. 400 30 16 1.5 0.01 0.01 0.2 2 0.1 5 1.2 1.2 MAX. 500 50 20 2 2.4 10 1 5 20 1 100 2.2 2.2 UNIT V V V V V A mA mA mA A A V V
DYNAMIC CHARACTERISTICS
Tmb = 25 C unless otherwise specified SYMBOL V(CL)CER PARAMETER CONDITIONS MIN. 350 TYP. 400 MAX. 500 UNIT V
Collector-emitter clamp voltage RG = 1 k; IC = 10 A; (peak value) -40 Tj 150C; Inductive load; see Figs. 23,24 Forward transconductance Input capacitance Output capacitance Feedback capacitance Turn-off delay time Fall time Crossover Time Turn-off Energy loss VCE = 15 V; IC = 4 A VGE = 0 V; VCE = 25 V; f = 1 MHz
gfe Cies Coes Cres td off tf tc Eoff
5.5 -
15 940 95 30 13 6 12 13
20 1200 130 50 18 10 -
S pF pF pF s s s mJ
IC = 8 A; VCL = 300 V; RG = 1 k; VGE = 5 V; Tj = 125C; Inductive load; see Figs. 20,21
December 1996
2
Rev. 1.100
Philips Semiconductors
Product specification
Insulated Gate Bipolar Transistor Protected Logic-Level IGBT
BUK866-400 IZ
1E+01
Zth(j-mb) / (K/W)
120 110 100 90 80 70 60 50 40
P D t p t D= p T
PD%
Normalised Power Derating
1E+00
D= 0.5 0.2
1E-01
0.1 0.05 0.02
1E-02
0
30 20 10 0
1E+01
t T
1E-03 1E-07
1E-05
1E-03 t/s
1E-01
0
20
40
60
80 100 Tmb / C
120
140
Fig.1. Transient thermal impedance Z th j-mb = f(t) ; parameter D = tp/T
IC / A I CLM 10 BUK8Y6-400IZ
Fig.4. Normalised power dissipation. PD% = 100.PD/PD 25C = f(Tmb)
ICLM / A BUK8Y6-400IZ
15
10
Self-clamped 1
5
0.1 0 200 VCE / V 400 600
0 0 50 100 150 dVCE/dt (V/us) 200
Fig.2. Turn-off Safe Operating Area conditions: Tj Tjmax. ; RG 1 k
VCE / V
Tj / C = 150 25 -40
Fig.5. Derating of ICLM with turn-off dVCE/dt conditions: VCE 500 V; Tj Tjmax.
VCE / V
150 Tj / C = 25 -40
3
PMG35A
2
PMG35A
1.5
2
1
1
0.5
0 0 4 8 12 16 IC / A 20 24
0 0 4 8 12 16 IC / A 20 24
Fig.3. Typical On-state Voltage VCEsat = f(IC); parameter Tj; conditions: VGE = 3.5 V
Fig.6. Typical On-state Voltage VCEsat = f(IC); parameter Tj; conditions: VGE = 5 V
December 1996
3
Rev. 1.100
Philips Semiconductors
Product specification
Insulated Gate Bipolar Transistor Protected Logic-Level IGBT
BUK866-400 IZ
30
IC / A 5 4
PMG35A VGE / V = 4 3
1E-2 1E-3 IE-4
+/- IGES / A
PMG35A
20 2.8 2.6 10 2.4 2.2 2 0 0 2 4 VCE / V 6 8 10
1E-5 1E-6 1E-7 1E-8 1E-9 0 5 10 VGE / V 15 20
Fig.7. Typical Output Characteristics IC = f(VCE); parameter VGE; conditions: Tj = 25C
IC / A
150 Tj / C = 25 -40
Fig.10. Typical gate-emitter charcteristics IGES = f(VGE); conditions: VCE = 0 V; Tj = 25C
ICES / mA
150 Tj / C = 25 -40
30
PMG35A
10
PMG35A
20
1
10
0 0 1 2 VGE / V 3 4
0.1 350
370
390 410 VCE / V
430
450
Fig.8. Typical Transfer Characteristics IC = f(VGE), parameter Tj; conditions: VCE = 10 V
gfe / S PMG35A
Fig.11. Typical collector clamp characteristics ICES = f(VCE); parameter Tj; conditions: VGE = 0 V
35 30 25 20
2.5
VGE(TO) / V
BUK856-400IZ
2
max.
1.5
15 10 5 0 0
Tj / C = 150 25 -40
typ.
1
min.
10 IC / A
20
30
0.5 -40 -20 0 20 40 60 Tj / C 80 100 120 140
Fig.9. Typical Forward Transconductance gfe = f(IC); parameter Tj; conditions: VCE = 10 V
Fig.12. Gate Threshold Voltage VGE(TO) = f(Tj); conditions: IC = 1 mA; VCE = VGE
December 1996
4
Rev. 1.100
Philips Semiconductors
Product specification
Insulated Gate Bipolar Transistor Protected Logic-Level IGBT
BUK866-400 IZ
1E-01
IC / A
SUB-THRESHOLD CONDUCTION
100
t / us, E / mJ
PMG35A
1E-02 2% 98 %
td(off) E(off)
typ
1E-03
10
1E-04
tf
1E-05
1E-06 0 0.4 0.8 1.2 VGE / V 1.6 2 2.4
1 0 1 2 3 Rg / kOhm 4 5
Fig.13. Sub-threshold collector current IC = f(VGE); Tj = 25C; VCE = VGE
VGE / V PMG35A
Fig.16. Typical Switching Characteristics vs. RG conditions: Tj=125 C; IC=8 A; VCL=300 V; LC=5 mH.
t / us, E / mJ 15 PMG35A
6 5
Vcc / V = 12
4
td(off)
300
3 2 1 0 0 10 20 Qg / nC 30
10
E(off)
5
tf
0 0 50 Tj / C 100 150
Fig.14. Typical Turn-on Gate Charge Characteristics VGE = f(QG); conditions: IC = 8 A.
C / pf pmg35a
Fig.17. Typical Switching Characteristics vs. Tj conditions: IC=8 A; VCL=300 V; RG=1 k; LC=5 mH.
t / us, E / mJ 15
td(off)
10000
PMG35A
1000
Cies
10
tf
100
Coes
5
10 0.01 0.1 1 10 VCE / V 100
Cres
0 0
E(off)
1000
2
4 IC / A
6
8
10
Fig.15. Typical Capacitances Cies, Coes, Cres C = f(VCE); conditions: VGE = 0 V; f = 1 MHz
Fig.18. Typical Switching Characteristics vs. IC conditions: Tj=125 C VCL=300 V; RG=1 k; LC=5 mH.
December 1996
5
Rev. 1.100
Philips Semiconductors
Product specification
Insulated Gate Bipolar Transistor Protected Logic-Level IGBT
BUK866-400 IZ
150
dVce/dt (V/us)
PMG35A
35
V(BR)ECS / V
BUK856-400IZ
typ.
100
30
50
25 min.
0 0 1 2 3 Rg / kOhm 4 5
20 -50
0
50 Tj / degC
100
150
Fig.19. Typical Turn-off dVCE/dt vs. RG conditions: Tj=125 C; IC=8 A; VCL=300 V; LC=5 mH.
Vcc
Fig.22. Reverse Breakdown Voltage V(BR)ECS = f(Tj); conditions: IEC = 50 mA
Vcc
Lc t p : adjust for correct Ic V CL
Lc t p : adjust for correct Ic
D.U.T. RG
VGE
IC measure
D.U.T. RG
VGE
IC measure
0V
0R1
0V
0R1
Fig.20. Test circuit for inductive load switching times.
Fig.23. Test circuit for clamped turn-off energy test
I 90%
C
I
Ic
tf td(off)
V Vce t V(cl)cer
10% t 90% VGE tc
P Vce x Ic
VCE
Vge
t
10% t
Ecer t
Fig.21. Definitions of inductive load switching times.
Fig.24. Definition of clamping energy ECER
December 1996
6
Rev. 1.100
Philips Semiconductors
Product specification
Insulated Gate Bipolar Transistor Protected Logic-Level IGBT
MECHANICAL DATA
Dimensions in mm Net Mass: 1.4 g
10.3 max 4.5 max 1.4 max
BUK866-400 IZ
11 max 15.4
2.5 0.85 max (x2) 2.54 (x2)
0.5
Fig.25. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5 2.0
3.8
5.08
Fig.26. SOT404 : soldering pattern for surface mounting.
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8".
December 1996
7
Rev. 1.100
Philips Semiconductors
Product specification
Insulated Gate Bipolar Transistor Protected Logic-Level IGBT
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
BUK866-400 IZ
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
December 1996
8
Rev. 1.100

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